1. Field of the Invention
The present invention relates to a wiring substrate where a plurality of projection electrodes are arranged within an electrode formation region on a substrate main surface, and to a manufacturing method for the same.
2. Description of Related Art
In the related art, a wiring substrate (i.e., semiconductor package) formed by installing a component such as an IC chip is well known. Here, as a structure for enabling electrical connection to the IC chip, it has been proposed that a solder bump be formed on a plurality of connecting terminals arranged at the bottom surface side of the IC chip or on a pad (i.e., C4 pad: Controlled Collapsed Chip Connection Pad) which is a plurality of projection electrodes arranged on a substrate main surface of the wiring substrate. For example, see JP-A-2010-226075, specifically FIG. 19A and the like, and JP-A-1995-211722, specifically FIG. 4 and the like.